Double data rate (DDR) is a standard for connecting between a CPU (controller) and an external memory (dual inline memory module (DIMM)), and the DDR4 standard has been established in accordance with an increase in operation speed.
In DDR4, it has been decided that an interface called Pseudo Open Drain (POD) is employed as an interface technology for data transmission. The POD interface has a form in which a terminal resistor is connected between a signal terminal and a power source for a CMOS output. Thus, an output voltage (an input voltage) becomes a High (H) potential equal to a power source voltage (VDDQ), or a Low (L) potential equal to a voltage that is obtained by dividing VDDQ by a ratio of the terminal resistance and an output impedance of an output buffer.
In order for a controller to perform writing and reading of data to and from a memory, data strobe signals called DQS and data signal called DQ are transmitted and received between the controller and a DIMM. When data is written to the memory (during a write operation), data strobe signals and a data signal are transmitted from the controller to the DIMM. When data is read from the memory (during a read operation), data strobe signals and a data signal are transmitted from the DIMM to the controller. In addition to the data strobe signals and the data signal, address signals and command signals by which the controller specifies an operation (write/read) to/from the memory are provided, and these signals are uni-directionally transmitted from the controller to the DIMM.
The data strobe signals (DQS) are differential signals and include normal phase DQS_t and inverted phase DQS_c. The logic levels of DQS_t and DQS_c outputted from a DQS driver (an output circuit) of the controller and the DIMM are signals inverted with respect to each other at all times, and the logic values thereof are determined by the relative potentials of DQS_t and DQS_c. Specifically, a condition of DQS_t>DQS_c results in “H”, a condition of DQS_t<DQS_c results in “L”, and a condition of DQS_t=DQS_c results in an undefined state. The undefined state refers to “H”, “L”, or a state between both.
The data signal (DQ) is single-ended, and determination of the logic value thereof depends on a potential relative to a common voltage.
During a write operation and/or a read operation, the receiving side of the data signal (the memory during the write operation, and the controller for the read operation) utilizes the data strobe signals (DQS) as a timing reference for the data signal (DQ) to receive data. Therefore, the received data strobe signals (DQS) are supplied to a circuit that acquires the data signal (DQ) and, a situation where the data signal (DQ) is not acquired may occur when there is a large delay in a receiving circuit that receives the data strobe signals (DQS). DDR4 is a high-speed memory interface, and a delay is thus desired to be small in the receiving circuit that receives the data strobe signals (DQS).
When writing and reading to and from the memory are not performed, the controller and the DIMM output neither data strobe signals (DQS) nor data signal (DQ). Therefore, in DDR4, both data strobe signals (DQS) and data signal (DQ) become “H” due to the terminal resistor. In particular, because both DQS_t and DQS_c become “H”, the logic value of the data strobe signals (DQS) is not defined, that is, becomes undefined. In an undefined state of the data strobe signals (DQS), malfunction is likely to occur when the data signal (DQ) is acquired and transferred inside due to noise and the like.
In a high-speed memory interface circuit, it is desirable that there be no such malfunction in which a data signal transmitted in synchronization with differential data strobe signals (DQS) is erroneously acquired.
The following is a reference document.
[Document 1] Japanese Laid-open Patent Publication No. 2000-115259.